log in | register | forums
Show:
Go:
Forums
Username:

Password:

User accounts
Register new account
Forgot password
Forum stats
List of members
Search the forums

Advanced search
Recent discussions
- Code GCC produces that makes you cry #12684 (Prog:27)
- LEAF - game for A3010 released at last! (Games:1)
- GPS becomes Data Logger (News:1)
- RISC OS source code to be ...Apache open source license (News:13)
- Geminus (Gen:14)
- RISC OS London Show Report 2018 (News:5)
- October News Headlines (News:)
- RISC OS London Show 2018 - Notes from the talks (News:4)
- Does this form of documentation annoy you as much as me? (Prog:1)
- RISC OS London Show 2018 - pictures (News:)
Latest postings RSS Feeds
RSS 2.0 | 1.0 | 0.9
Atom 0.3
Misc RDF | CDF
Site Search
 
Article archives
The Icon Bar: Programming: Does this form of documentation annoy you as much as me?
 
  Does this form of documentation annoy you as much as me?
  Stoppers (17:51 29/10/2018)
 
Simon Willcocks Message #124363, posted by Stoppers at 17:51, 29/10/2018
Member
Posts: 284
From the ARM ARM for ARMv8: ARM DDI 0487B.a

MIOCNCE, bit [38]

Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1&0 translation
regime.

0 For the Non-secure EL1&0 translation regime, for permitted accesses to a memory
location that use a common definition of the Shareability and Cacheability of the
location, there must be no loss of coherency if the Inner Cacheability attribute for those
accesses differs from the Outer Cacheability attribute.

1 For the Non-secure EL1&0 translation regime, for permitted accesses to a memory
location that use a common definition of the Shareability and Cacheability of the
location, there might be a loss of coherency if the Inner Cacheability attribute for those
accesses differs from the Outer Cacheability attribute.

Couldn't they write:

MIOCNCE, bit [38]

Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1&0 translation
regime.

For the Non-secure EL1&0 translation regime, for permitted accesses to a memory
location that use a common definition of the Shareability and Cacheability of the
location, if the Inner Cacheability attribute for those accesses differs from the
Outer Cacheability attribute:

0 there must be no loss of coherency

1 there might be a loss of coherency
  ^[ Log in to reply ]
 

The Icon Bar: Programming: Does this form of documentation annoy you as much as me?