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Over the summer V: Oh god not another Rocky movie |
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Holger Palmroth |
Message #79419, posted by Raeddie at 06:31, 29/8/2006, in reply to message #79346 |
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Have you had a look at PicoDrive?
Since it's 68000 emulation is in ARM assembly I'd hope it could play Megadrive games like Sonic 2 and Micro Machines at full speed on an Iyonix.  Hmm... Can that Emulator gain any decent speed on RISC OS? One of the limiting factors on earlier Emulators were the different endianess of ARM and 68000. I know that modern ARMs can change to big endian byte order, but I doubt this feature is usable under RISC OS. |
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Jeffrey Lee |
Message #79428, posted by Phlamethrower at 10:56, 29/8/2006, in reply to message #79416 |
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Well, I've done some 68K assembler, but really if you can get the state of the emulator after each instruction, it should be pretty easy to track down what's broken if it fails after so few cycles. Yeah. I was hoping to add some code that would display the state before/after each instruction, but to do it properly (i.e. so that I can understand what's going on) I'd have to branch into C so I can use the disassembler, which would probably result in more problems. Instead, I think I'll have a go at hacking it to only execute one instruction at once, even if this runs the risk of magically fixing whatever is wrong. |
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Jeffrey Lee |
Message #79429, posted by Phlamethrower at 11:01, 29/8/2006, in reply to message #79419 |
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Hmm... Can that Emulator gain any decent speed on RISC OS? One of the limiting factors on earlier Emulators were the different endianess of ARM and 68000. I know that modern ARMs can change to big endian byte order, but I doubt this feature is usable under RISC OS. The emulator byte swaps all the memory, so no per-access byte swapping is required |
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Jeffrey Lee |
Message #79435, posted by Phlamethrower at 12:03, 29/8/2006, in reply to message #79352 |
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And then hope that the Iyonix memory bus supports LDRH/STRH! Yes, of course it does. Apparently it can even transfer whole words of data.
You lie!
ldrsh r0,[r4]
= complete randomness
ldrh r0,[r4]
mov r0,r0,lsl #16
mov r0,r0,asr #16
= complete randomness
ldrb r0,[r4]
ldrb r8,[r4,#1]
orr r0,r0,r8,lsl #8
mov r0,r0,lsl #16
mov r0,r0,asr #16
= works perfect
I've checked the disassembly, and 'as' is producing the right opcodes (Unless the disassembler StrongED is using is broken). So how do you explain that, then?  |
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Jeffrey Lee |
Message #79438, posted by Phlamethrower at 12:19, 29/8/2006, in reply to message #79435 |
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And yet the instructions work perfectly in BASIC. Wah! |
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Phil Mellor |
Message #79439, posted by monkeyson2 at 12:20, 29/8/2006, in reply to message #79435 |
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Even I knew that the Risc PC didn't support those instructions. |
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Phil Mellor |
Message #79440, posted by monkeyson2 at 12:22, 29/8/2006, in reply to message #79435 |
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I've checked the disassembly, and 'as' is producing the right opcodes (Unless the disassembler StrongED is using is broken). So how do you explain that, then? http://groups.google.co.uk/group/comp.sys.acorn.programmer/msg/201ff33daa0e0190?dmode=source&hl=en |
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Jeffrey Lee |
Message #79441, posted by Phlamethrower at 12:31, 29/8/2006, in reply to message #79439 |
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Even I knew that the Risc PC didn't support those instructions. As do I (also after testing them myself to confirm it)
Which is why I'm doing this on an Iyonix, which, according to adrian, should support them. BASIC was extended to support the full instruction set of the CPU - what's the point in that if they don't work properly?  |
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Phil Mellor |
Message #79444, posted by monkeyson2 at 13:24, 29/8/2006, in reply to message #79441 |
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Which is why I'm doing this on an Iyonix, which, according to adrian, should support them. BASIC was extended to support the full instruction set of the CPU - what's the point in that if they don't work properly? Why include it in the RISC OS 4 assembler, then?
I think I remember reading somewhere that LDRH/STRH halfword transfers worked on the Iyonix podule bus. |
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Jeffrey Lee |
Message #79445, posted by Phlamethrower at 13:39, 29/8/2006, in reply to message #79444 |
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Which is why I'm doing this on an Iyonix, which, according to adrian, should support them. BASIC was extended to support the full instruction set of the CPU - what's the point in that if they don't work properly? Why include it in the RISC OS 4 assembler, then?
Maybe they were added while Phoebe was still in development. And in any case, they're only enabled via an OPT setting. In RO 5, they seem to be enabled all the time.
I think I remember reading somewhere that LDRH/STRH halfword transfers worked on the Iyonix podule bus. So why won't they work when I want them to? |
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Richard Wilson |
Message #79446, posted by not_ginger_matt at 14:00, 29/8/2006, in reply to message #79445 |
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Maybe they were added while Phoebe was still in development. And in any case, they're only enabled via an OPT setting. In RO 5, they seem to be enabled all the time.
I think I remember reading somewhere that LDRH/STRH halfword transfers worked on the Iyonix podule bus. So why won't they work when I want them to? They should do -- Tinct can be assembled to use halfword access to get a bit of speed gain in 16bpp modes and this certainly worked with the Omega it was written on. I'm pretty sure early test versions with this setting were also used by Iyonix owners without problems.
The only things I can think of is that your address isn't half-word aligned or that it's the signed instruction that's sending things a bit loopy (does a plain LDRH/STRH work?)
[Edited by not_ginger_matt at 14:00, 29/8/2006] |
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Jeffrey Lee |
Message #79453, posted by Phlamethrower at 14:39, 29/8/2006, in reply to message #79446 |
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The only things I can think of is that your address isn't half-word aligned or that it's the signed instruction that's sending things a bit loopy (does a plain LDRH/STRH work?) The address that's failing is word aligned, and LDRH fails too  |
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Phil Mellor |
Message #79455, posted by monkeyson2 at 14:46, 29/8/2006, in reply to message #79446 |
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this certainly worked with the Omega it was written on. Whatwhatwhatwhatwhat? You own an Omega?  |
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JMB |
Message #79456, posted by jmb at 14:52, 29/8/2006, in reply to message #79453 |
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The only things I can think of is that your address isn't half-word aligned or that it's the signed instruction that's sending things a bit loopy (does a plain LDRH/STRH work?) The address that's failing is word aligned, and LDRH fails too
Hm. What address is it attempting to read from? |
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Jeffrey Lee |
Message #79462, posted by Phlamethrower at 15:28, 29/8/2006, in reply to message #79456 |
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It should be 000D6ADC.
Code + brief instructions are now available here for those who are feeling adventurous. |
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Jeffrey Lee |
Message #79464, posted by Phlamethrower at 15:31, 29/8/2006, in reply to message #79462 |
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Actually with the code I just uploaded it will be 000D6AD8 (assuming you have the same version of GCC as me ). It actually loads from that address twice before sending the 68000 off into lala-land, each result gets a different answer. (Neither of which appear to be correct) |
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Phil Mellor |
Message #79465, posted by monkeyson2 at 15:49, 29/8/2006, in reply to message #79464 |
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Couldn't you just replace them with an LDR and a shift? |
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Jeffrey Lee |
Message #79466, posted by Phlamethrower at 15:54, 29/8/2006, in reply to message #79465 |
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Yes, there isn't really much code that would need changing.
But the issue is that, as far as we know, we shouldn't need to remove LDRH/STRH to get it to work. |
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Adrian Lees |
Message #79471, posted by adrianl at 16:10, 29/8/2006, in reply to message #79466 |
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I'll try to look at this later, but LDR(S)H is fine on the Iyonix; I use it all the time. One thing to be aware of is that it doesn't rotate like LDR does, ie. it actually just reads from (addr & ~1).
Beyond that, there's something wrong with your code and/or assumptions; without trawling that archive I'd need you to elaborate on what you're doing or post a simple test case. Sorry.
Edit: okay, I'll mention one other possibility too, but I think it highly unlikely, so please don't latch onto this as the explanation. Lazy-task swapping can legitimately cause any LDR(H/ instruction to abort. I'm not sure whether the aborted instruction is simply restarted or whether it's emulated in the abort handler, but clearly if LDRH isn't handled properly this could give problems.
[Edited by adrianl at 16:32, 29/8/2006] |
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Phil Mellor |
Message #79472, posted by monkeyson2 at 16:15, 29/8/2006, in reply to message #79464 |
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Yes, but does it work IF you change them to different instructions? It's not something silly like not making the Wimpslot big enough? (Not that I'd ever do something like that in any of my debugging sessions, oh no) |
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Jeffrey Lee |
Message #79475, posted by Phlamethrower at 16:39, 29/8/2006, in reply to message #79471 |
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I'll try to look at this later, Yay!
but LDR(S)H is fine on the Iyonix; I use it all the time. Also yay! (Present case excepted)
One thing to be aware of is that it doesn't rotate like LDR does, ie. it actually just reads from (addr & ~1). Shouldn't be a problem, I think.
Beyond that, there's something wrong with your code and/or assumptions; without trawling that archive I'd need you to elaborate on what you're doing or post a simple test case. Sorry. It's not my code, which is partly why I don't want to piss around changing it, because it will make it that much harder to upgrade to a new version of the code.
There are reproduction steps and an excerpt of the broken routine in the readme file. But I'm off to my parents place in a couple of hours, so don't have time to wittle it down to a smaller test case.
Edit: okay, I'll mention one other possibility too, but I think it highly unlikely, so please don't latch onto this as the explanation. Lazy-task swapping can legitimately cause any LDR(H/ instruction to abort. I'm not sure whether the aborted instruction is simply restarted or whether it's emulated in the abort handler, but clearly if LDRH isn't handled properly this could give problems. I am running the code from a taskwindow, but it also showed the same problem when I ran it from the command line.
Yes, but does it work IF you change them to different instructions? Yes
It's not something silly like not making the Wimpslot big enough? (Not that I'd ever do something like that in any of my debugging sessions, oh no)
No. It's trying to read from the 68000 ROM, and I think I would have noticed if there wasn't enough memory to load that |
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Phil Mellor |
Message #79477, posted by monkeyson2 at 17:32, 29/8/2006, in reply to message #79475 |
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There are reproduction steps and an excerpt of the broken routine in the readme file. But I'm off to my parents place in a couple of hours, so don't have time to wittle it down to a smaller test case. And you're going because you think they'll be able to help? |
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Adrian Lees |
Message #79478, posted by adrianl at 17:34, 29/8/2006, in reply to message #79477 |
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There are reproduction steps and an excerpt of the broken routine in the readme file. But I'm off to my parents place in a couple of hours, so don't have time to wittle it down to a smaller test case. And you're going because you think they'll be able to help?
10 minute after he's left, he'll realise what the problem is |
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Jeffrey Lee |
Message #79479, posted by Phlamethrower at 17:36, 29/8/2006, in reply to message #79478 |
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I hope so |
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JMB |
Message #79499, posted by jmb at 23:18, 29/8/2006, in reply to message #79462 |
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Posts: 467
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Looking at the disassembly for Op51c8 (The code that handles 51c8, 51c9, etc. opcodes) you'll see the following:
...
;@ Get Branch offset:
ldrsh r0,[r4]
...
Actually, no you won't. If you'd looked at the disassembly, you'd have seen:
...
ldrsh r0,[r4,r0]
...
So, congratulations, you've found yet another bug in AS. |
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Adrian Lees |
Message #79501, posted by adrianl at 23:35, 29/8/2006, in reply to message #79499 |
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So, congratulations, you've found yet another bug in AS. But the good news is: |
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Michael Drake |
Message #79506, posted by tlsa at 00:35, 30/8/2006, in reply to message #79501 |
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Yay! Pretty much everything I tried worked, apart from Sonic 2 in the actual levels. It looks fast enough too. |
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Michael Drake |
Message #79508, posted by tlsa at 00:52, 30/8/2006, in reply to message #79506 |
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The other thing I've noticed is that on the Sonic 1 title screen, Sonic appears above the banner.
http://www.squish.net/generator/shots.html says it's because the emulator does not have the Megadrive hardware limit of only displaying a certain number of sprites per scanline. |
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JMB |
Message #79509, posted by jmb at 01:55, 30/8/2006, in reply to message #79499 |
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So, congratulations, you've found yet another bug in AS. Which I've now fixed; the next release of GCC (should be imminent) will contain this. |
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Adrian Lees |
Message #79511, posted by adrianl at 04:30, 30/8/2006, in reply to message #79501 |
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I've uploaded modified code including assembler-ified raster conversion (with optional horizontal interpolation + vertical doubling) to http://adrian.aemulor.com/downloads/pico.zip
There's also prototype code in there to drive Tinct or my smooth-filtered code, neither of which - alas - is fast enough to scale to 200% (640x480, ie. 4 times as many output pixels) at video rates, so it's disabled for now.
I also made a few small tweaks, mainly instruction sequencing, to the Cyclone emulator core, largely for my own amusement.
More to follow, perhaps..... but I really shouldn't have been doing all that this evening  |
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